The fetch-decode-execute cycle is the fundamental cycle that a CPU operates on. Registers play a crucial role in each stage of this cycle:

1. Fetch: The Program Counter (PC) holds the address of the next instruction to be fetched from memory. The address in the PC is used to access the instruction in memory, and the instruction is loaded into the Instruction Register (IR). The PC is then incremented to point to the next instruction.
2. Decode: The instruction in the Instruction Register (IR) is decoded to determine the operation to be performed. This decoding process often involves using the IR's contents to identify the opcode and any operands. The decoded information may be used to select which registers will be used as source or destination operands.
3. Execute: The operation specified by the decoded instruction is performed. This often involves reading data from registers (operands), performing calculations, and storing the results back into registers. The Memory Address Register (MAR) might be used to access memory for data or to store results. The Memory Data Register (MDR) is used to hold the data being read from or written to memory. The Status Register (SR) is updated to reflect the outcome of the operation (e.g., setting the zero flag if the result is zero). The Program Counter (PC) is updated to point to the next instruction, which may be the next instruction in sequence or a different address based on a branch instruction.

Example: Consider an instruction to add two numbers stored in registers R1 and R2, and store the result in register R3. The PC fetches the instruction. The IR contains the instruction. The instruction is decoded to identify the addition operation and the registers R1, R2, and R3 as operands. The values from R1 and R2 are read into the CPU's internal arithmetic logic unit (ALU). The ALU performs the addition. The result is then stored in R3. Finally, the PC is incremented to point to the next instruction.

Here's a breakdown of the interrupt handling process for a keyboard press:

1. Interrupt Signal: The keyboard controller generates an interrupt signal and asserts it on the CPU's interrupt line.
2. Interrupt Acknowledgment: The CPU acknowledges the interrupt signal. This typically involves the CPU finishing the current instruction and saving the current state of the processor.
3. Interrupt Vector Lookup: The CPU uses the interrupt line to determine the interrupt vector associated with the keyboard. This vector is used to index into the IDT.
4. Interrupt Descriptor Retrieval: The CPU fetches the interrupt descriptor from the IDT using the interrupt vector as the index.
5. Saving CPU State: The CPU pushes the current state of the processor (e.g., program counter, registers) onto the stack. This is crucial for returning to the interrupted program later.
6. Executing the ISR: The CPU loads the address of the ISR (obtained from the interrupt descriptor) into the program counter and transfers control to the ISR.
7. ISR Execution: The ISR performs the necessary actions, such as reading the keycode from the keyboard controller's buffer.
8. Restoring CPU State: Before returning from the ISR, the ISR restores the saved CPU state from the stack.
9. Return from Interrupt: The ISR executes a special instruction (e.g., IRET in x86) to return control to the interrupted program. This instruction pops the saved CPU state from the stack.
10. Resuming Execution: The CPU resumes execution of the interrupted program from the point where it was interrupted.

The CPU's stack is essential for saving and restoring the processor's state during interrupt handling. This ensures that the interrupted program can resume execution correctly after the interrupt has been handled.

A stored program is a program that is stored in the computer's memory along with the data it operates on. Instead of being hardwired into the hardware (as in earlier computers), the instructions that make up the program are represented as binary code and stored in memory. The CPU then fetches these instructions from memory and executes them.

The stored program concept is fundamental to the Von Neumann architecture. The shared memory space allows the program instructions to be treated as data. The CPU's instruction fetch cycle involves fetching instructions from memory, which are then interpreted and executed. This eliminates the need for physical rewiring of the computer to change its behavior – a major advancement over earlier mechanical computers.

Example: Addition Program

Consider a simple program to add two numbers stored in memory. The program might be represented in assembly language as follows (simplified):

LOAD A, 10   ; Load the value 10 into register A
LOAD B, 5    ; Load the value 5 into register B
ADD A, B     ; Add the value in register B to register A
STORE A, Result ; Store the result in memory location 'Result'

These instructions are stored in memory as binary code. When the program is executed, the CPU fetches each instruction from memory, decodes it, and performs the corresponding operation. The program's instructions are not fixed; they can be changed simply by modifying the binary code stored in memory.